Note: this article was first written for the German edition of Linux Magazineand was later posted in the English edition too. We negotiated the right to publish it on our blog after the print editions. Here is the original version the paper versions were modified by the editors to make them more concise.
In the family tree of computers, personal computers PCs are the parents, while the children and teenagers are mobile devices. PCs are no longer physically attractive, getting close to retirement. They produce a lot of heat, and make all sorts of unpleasant noise when you are next to them. Noise is caused by keyboard presses, by fans that are essential to avoid computer meltdown, and by rotating disks that sound like nothing but something that rotates.
The last chance for this generation to survive a few more years is to send them to a remote place where nobody can see their old bodies and hear their annoying noise any more.
This place is called The Cloud. Perhaps because it gets these systems closer to the final destination: heaven. Most modern devices have flash storage, and most of these devices run Linux.
Managing flash storage with Linux
This article gives technical details about how Linux supports flash storage devices. It should mostly interest people creating embedded and multimedia devices using the Linux kernel to get the best performance out of their hardware.
People who wish to hack the devices they own should be interested too. Flash storage, also called solid state, has multiple advantages over rotating storage. First, the absence of mechanical and moving parts eliminate noise, increase reliability and resistance to shock and vibrations, and also reduces heat dissipation as well as power consumption. Second, random access to data is also much faster, as you no longer have to move a disk head to the right location on the medium, which can take milliseconds.
Flash also has its shortcomings, of course. First, for the same price, you have about 10 times less solid state storage than rotating storage. This can be an issue with operating systems that require Gigabytes of disk space. Fortunately, Linux only needs a few MB of storage. Second, writing to flash storage has special constraints. This constraint can also cause write speed to be much lower than read speed.
Third, flash blocks can only withstand a rather limited number of erases from a few thousand for today densest NAND flash to one million at best. NOR flash was the first type of flash storage that was invented.The minimum amount of the required storage would be 1 MiB 8 Mbit to fit a user friendly bootloader with some advanced features.
This is non-negligible, but might be still worth it at least to avoid the frustrated "I plugged the power but there is nothing on the monitor" support requests from inexperienced users.Nuw song download
The primary use for this additional space would be a storage of some size reduced Linux kernel together with a small Buildroot generated compressed initrd image. As for the provided functionality, it can do some hardware diagnostic self-tests and even update itself over Internet.
The table below lists the exact pins for different SoC variants and some additional notes:. Each of these commands is encoded in 4 bytes 1 byte for the command id and 3 bytes for the address. The first command reads bytes from the address 0. If a valid eGON header is recognized, then a sequence of commands reading byte blocks is done next.
USB NAND FLASH DISK USB Device - driver download software
The first byte block is read from the address 0, the second byte block is read from the address and this continues until the whole first stage bootloader is transferred. Here the BROM tries to read a valid first stage bootloader starting from page number 0, 32, 64, 96, and It only reads the first bytes from every page.
Since it simply sends the standard SPI NAND flash commands, it is a good idea to use a flash with ECC turned on by default and is performed by the flash itself, since errors cannot otherwise be corrected.
But the timing constraints are too tight to do a perfect emulation. A perfect emulation would need to correctly handle the Read Data Bytes command, which means that after the last bit of the address is received, the first bit of data from that address needs to be served back in the next SPI cycle. With such a protocol, we can't benefit from any kind of receive and transmit buffering and make use of the hardware SPI controller.
This time is comparable to the DRAM access latency, so we are in a big trouble if we get any L2 cache misses though this can be mitigated by prefetching the right cache line after receiving just enough of the address bits. So a simplistic approach is just to use the SPI controller hardware, ignore any received commands and stream the data according to the expected pattern. That would be 4 padding bytes, then initial bytes of the firmware, then 4 bytes padding again and initial bytes of the firmware, etc.
This was only a method get some information about the BROM behaviour. While there are no known boards with built-in SPI flash, it is still possible to arrange some test setup.
The SPI0 pins are often available on the expansion headers. The wires are entangled and tied in a knot, with the SPI flash module being more or less fixated in place and sticking upwards. Not a very aesthetically pleasing sight, but it works fine for testing the software. The basic SPI boot support is available since vThis documentation is provided for developers who want to implement board drivers or filesystem drivers suitable for NAND devices.
The function and structure docs are autogenerated. Each function and struct member has a short description which is marked with an [XXX] identifier.
The following chapters explain the meaning of those identifiers. The functions are marked with [XXX] identifiers in the short comment.
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The identifiers explain the usage and scope of the functions. Following identifiers are used:. They are not replaceable and provide functionality which is complete hardware independent.
Generic functions are not replaceable and provide functionality which is complete hardware independent. Default functions provide hardware related functionality which is suitable for most of the implementations.
These functions can be replaced by the board driver if necessary. Those functions are called via pointers in the NAND chip description structure. The struct members are marked with [XXX] identifiers in the comment. The identifiers explain the usage and scope of the members. These members are for NAND driver internal use only and must not be modified.
Replaceable members hold hardware related functions which can be provided by the board driver. Board specific members hold hardware related information which must be provided by the board driver. Optional members can hold information relevant for the board driver.12 protek rc dustbuster 2 xb8 2017 low profile pre
The generic NAND driver code does not use this information. For most boards it will be sufficient to provide just the basic functions and fill out some really board dependent members in the nand chip description structure.
If you want to divide your device into partitions, then define a partitioning scheme suitable to your board. The hardware control function provides access to the control pins of the NAND chip s. The access can be done by GPIO pins or by address lines. If you use address lines, make sure that the timing requirements are met. Address lines based example. The init function allocates memory and sets up all the board specific parameters and function pointers.
This function tries to detect and identify then chip.Flash memory is rewritable storage that does not need power supply to hold information. Flash memory banks are usually organized into sectors. Unlike conventional storage, writes to flash addresses have to be preceded by an erase of the corresponding locations.
Moreover, erases of portions of flash can be performed only at the granularity of individual sectors. Because of these constraints, flash memory is best used with device drivers and filesystems that are tailored to suit them.
On Linux, such specially designed drivers and filesystems are provided by the MTD subsystem. See All Related Store Items. When you push the power switch on your handheld, it's more than likely that it boots from flash memory. When you click some buttons to save data on your cell phone, in all probability, your data starts life in flash memory. Today, Linux has penetrated the embedded space and is no longer confined to desktops and servers. Linux avatars manifest in PDAs, music players, set-top boxes, and even medical-grade devices.
The Memory Technology Devices MTD subsystem of the kernel is responsible for interfacing your system with various flavors of flash memory found in these devices. This chapter uses the example of a Linux handheld to learn about MTD. This chapter is from the book. Related Resources Store Articles.
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What's Flash Memory? Looking at the Sources.Please, find here the table describing different characteristics of various NAND flashes. NAND flash is a sequential access device appropriate for mass storage applications, while NOR flash is a random access device appropriate for code storage application. NOR Flash can be used for code storage and code execution. It must be loaded into RAM memory and executed from there. Some facts about write speed.
They are very common in digital cameras and MP3 players. The card itself contains nothing smart at all.
It gets smart by software. The glue logic provides direct memory access to a small address window, which contains a boot loader stub, which loads the real boot code from the NAND device. The memory is arranged as an array of pages. Newer chips have Bytes data and and 64 Bytes spare area sizes. The spare area is used to store ECC error correction codebad block information and filesystem-dependent data. Erase is done on a per block basis.
Address is given by writing with the Address Latch Enable pin high. It's possible to use address lines for ALE and CLE, but you have to take care about the timing restrictions of the chip! Make sure, that they are logicaly combined with the corresponding chipselect.
As NAND flash uses a command driven programming and erasing, an accidental write or erase is not likely to happen. The consecutive writes to a page, before erasing it again, are restricted to writes, depending on the manufacturers specifications. This applies similar to the spare area. This makes it necessary for the filesystem to handle a writebuffer, which contains data, that is less than a page.
It is somewhat open under a non disclosure agreement with Toshiba, who owns all rights on this specifications. It's ok for multimedia applications. There are some efforts to implement it, but it's in an early stage. JFFS2 uses the default autoplacement scheme. The only JFFS2 specific usage of the oob area is the storage of the cleanmarker. The latest code is also available from GIT and daily snapshots.
The hardware dependent functions are provided by the hardware driver. They provide mainly the hardware access information and functions for the generic NAND driver. Most NAND chips actually available should be supported by the current code. The chip name does not longer contain cryptic part numbers, as the device ID is just an information about size, erase block size, pagesize and operating voltage.
The dark mode beta is finally here. Change your preferences any time. Stack Overflow for Teams is a private, secure spot for you and your coworkers to find and share information. I am using Yocto and meta-atmel to build an embedded Linux 4.
On my board is an Flash which is connected through SPI. I tried several ways to write on it. But they all failed. I've seen that before, refer to erasing-flash-nor-ioctlmemunlock-return-status. So, let's go step by step.
Your SPI NOR flash is described in the devicetree, and it seems you've managed to configure your kernel correctly that is, add the relevant drivers. This is confirmed by your log:. Now, in order to program the device you need to 1 erase the sectors you want to write, 2 write those sectors, and finally read back and confirm. To write, you can use a write syscall i. To erase you need an ioctl syscall, i. There was an error in my device tree table file.
The spi1, the image sensor interface isi1 and the i2c i2c1 where using the same pins. The SPI flash is mounted to mtdblock8 in your case. Use the below command to see all the existing partitions. This is very convenient to localize problem. Learn more.There is a way of using the spi kernel driver to work as a device in the userspace. It's called SPIdev. It is important to configure your. For the most boards SPI is disabled by default. To enable it you have to modify the device-tree of your board.
As an example, we will enable SPI0 for this board.Directx function error
Transfer size is limited to 64 bytes on sun4i and bytes on sun6i. You have to loop over longer messages in your code. Some SPI devices may require that you prefix each message fragment with a header, other may not.
Look up transfer diagrams in device datasheet. For info it is possible to use all the Hz frequency limit transfers, however bear in mind, that frequency will not scale linearly.
There are fixed frequencies you can select from, especially at the higher end:. If you are coding a driver for a SPI device, it makes most sense to code it as a kernel module.Hino code p204f
X you should register a new slave device and exchange data through it. There should be nodes like spi0, spi Number after spi is bus number. What number gets spi master depends on device-tree configuration.Demonstrating U-Boot from SPI/QSPI for 66AK2G
Here is an example of module, that writes 0x00 to SPI when module is initialized and 0xff when uninitialized. It is using bus number 0 and communicating at the speed of 1Hz:. Booting devices from SPI flash is covered in this other article. Moving that to the transfer function, hence, right before the transfer starts, mitigates that problem.
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